1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as MNOS (Metal Nitride Oxide Semiconductor) type EEPROM (Electrically Erasable and Programable Read Only Memory) and a method of manufacturing the same.
2. Description of the Related Art
The MNOS type EEPROM has a gate insulating film which has a thickness of about 2 to 3 nm and serves as a tunnel film formed under a gate electrode of an ordinary transistor; and a silicon nitride film formed on the gate insulating film.
A nonvolatile semiconductor memory device having a conventional, general MNOS type EEPROM structure as disclosed, for example, in "New Scaling Guidelines for MNOS Nonvolatile Memory Devices" by S. Minami et al., IEEE Transactions on Electron Devices, Vol. 38, No. 11, November, 1991, will be described below with reference to FIG. 10.
In FIG. 10, a memory cell of the nonvolatile semiconductor memory device has a first insulating film 3 formed on a P-type semiconductor substrate 1 to form a first gate insulating film in an active region separated by an element separation insulating films 2 formed on the P-type semiconductor substrate 1; N-type diffusion layer 9 which is formed in the P-type semiconductor substrate 1 on the opposite sides of the first insulating film 3; a silicon nitride film 6 formed on the first insulating film 3; a second gate insulating film 5 formed on the silicon nitride film 6; and an N-type polysilicon layer 8 formed on the second gate insulating film 5.
FIG. 11 shows a circuit equivalent to the memory cell. In FIG. 11, the reference numeral 18 designates a charge storage layer formed of the silicon nitride film 6; 21 is a source; 22 a drain; C1 a capacitance between the P-type semiconductor substrate 1 and the charge storage layer 18; C2 a capacitance between the N-type polysilicon layer 8 and the charge storage layer 18; and C3 a capacitance between the source 21 or drain 22 and the charge storage layer 18.
In the conventional nonvolatile semiconductor memory device, the silicon nitride film 6 is made thinner with miniaturization of the device and lowering of the program voltage, resulting in degradation of the retention characteristic of the silicon nitride film 6. As a countermeasure, the second insulating film 5 is formed on the silicon nitride film 6.
The writing and erasing operations of the conventional MNOS type EEPROM shown in FIG. 10 are carried out by transferring electrons between the P-type semiconductor substrate 1 and the silicon nitride film 6 through the whole region of the first gate insulating film 3. Accordingly, the writing and erasing efficiency becomes greater as the electron transmission region of the first gate insulating film 3 is made smaller.
In the nonvolatile semiconductor memory device having the Conventional MNOS type EEPROM structure as shown in FIG. 10, however, the gate length depends on processing accuracy in photolithography technique, so that the gate length is determined on the basis of the width of the first gate insulating film 3. Further, like in the case of a conventional MOS FET, the minimum gate length which causes a leak current is determined depending on the junction depth of the source/drain diffusion layers. Accordingly, the miniaturization of the nonvolatile memory device has a limit determined by the processing accuracy in photolithography technique and the junction depth of the source/drain diffusion layers.